`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    21:16:33 04/04/2013 
// Design Name: 
// Module Name:    databus 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module databus(
    input latchoe,
    input z80mreq,
	 input[7:0] latch,
    output[7:0] databus,
    output z80ramce
    );

// whenever the output latch is enabled or a memory request is made we need
// to output data from the latch or the RAM onto the bus

reg oe;
reg[7:0] db;

always@(posedge latchoe or negedge z80mreq)
	if (latchoe) begin
		oe = 1'b1;
		db = latch;
	end else begin
		oe = 1'b0;
		db = 8'bz;
	end

assign z80ramce = oe;
assign databus = db;

endmodule
